The present invention relates to a phase change memory device and a method for fabricating the same, and more specifically, to a phase change memory device employing a liner process for plating the phase change material.
Phase change material has a variety of applications in microelectronic devices such as optical storage media and solid state phase change memory devices. Phase change random access memory (PRAM) devices, for example, store data using a phase change material, such as, for example, a chalcogenide alloy, that transforms into a crystalline state or an amorphous state during cooling after a heat treatment. Each state of the phase change material has different resistance characteristics. Specifically, the phase change material in the crystalline state has low resistance and the phase change material in the amorphous state has high resistance. The crystalline state is typically referred to as a “set state” having a logic level “0”, and the amorphous state is typically referred to as a “reset state” having a logic level “1”. A current passed through the phase change material creates ohmic heating and causes the phase change material to melt. Melting and gradually cooling down the phase change material allows time for the phase change material to form the crystalline state. Melting and abruptly cooling the phase change material quenches the phase change material into the amorphous state. Currently, phase change materials are formed by various physical methods such as sputtering, chemical vapor deposition (CVD) and physical vapor deposition (PVD). Filling of vias within a phase change memory device at a high aspect ratio can be difficult. For example, the use of a PVD or CVD operation delivers material which may not reach the bottom surface of high aspect ratio vias.
Previously disclosed standard methods for plating include forming a seed layer (e.g., a liner) for the deposition of the phase change material. Although a chemical mechanical polishing could eliminate the excess material, it will not eliminate the short circuit path provided by the liner portion inside the cell, and thus the standard plating method will not be suitable for constructing a phase change memory cell. Other methods including forming a blanket seed layer along a bottom of the phase change material and then building the memory cell. However, if the seed layer is formed underneath all the memory cells, it may short circuit all of the bottom contacts in communication with the memory cells. Therefore, additional etching processes may have to be performed to isolate the memory cells, however, when attempting to shrink the dimensions it may be difficult to perform the latter step, and thus all the memory cells risk of being damaged by the RIE process or being connected together and may not act independently of each other.